Duty cycle comparator

ABSTRACT

A duty cycle comparator is described for comparing the duty cycles of two digital signals. The duty cycle comparator comprises a first controllable current source, a second controllable current source and a charge accumulation device. The comparator provides an output signal that is representative of the difference between the duty cycles independent of the frequency of the two digital signals.

FIELD OF THE INVENTION

The invention pertains to a duty cycle comparator to compare the dutycycles of two digital waveforms

SUMMARY OF THE INVENTION

In accordance with the principles of the invention a duty cyclecomparator has a first input coupled to a first node and a second inputcoupled to a second node to generate an output signal that representsthe difference in the duty cycles.

Further in accordance with the principles of the invention, the dutycycle comparator comprises a first controlled current source having acontrol input coupled to the first node, a second controlled currentsource having a control input coupled the second node, and a chargeaccumulation device coupled to the first and second controlled currentsources and to the first output node to generate the control signal. Inthe illustrative embodiment of the invention, the charge accumulationdevice is a capacitor.

BRIEF DESCRIPTION OF THE DRAWING

The invention will be better understood from a reading of the followingdetailed description of the drawing in which like reference designatorsare used to identify like elements in the various drawing figures, andin which:

FIG. 1 is block diagram of a prior art motor controller and fan;

FIG. 2 illustrates a portion of the prior art motor controller of FIG. 1in greater detail;

FIG. 3 is a diagram of a portion of a motor controller utilizing a dutycycle comparator in accordance with the principles of the invention;

FIG. 4 illustrates the duty cycle comparator of the controller of FIG. 3in greater detail;

FIGS. 5, 6, and 7 are waveforms showing the operation of the duty cyclecomparator of FIG. 4;

FIG. 8 is a more detailed diagram of a motor controller in accordancewith the principles of the invention; and

FIG. 9 illustrates steps in comparing duty cycles in accordance with theprinciples of the invention.

DETAILED DESCRIPTION

FIG. 1 illustrates a prior art closed loop voltage comparison typecontroller 100 and drive arrangement 109 for controlling the speed of aDC motor 101 that is utilized as part of a cooling fan assembly of acomputer which is not shown. An input PWM (Pulse Width Modulated) signalthat indicates the desired fan or motor speed is provided to aPWM-to-voltage converter 103. Converter 103 generates an output voltagethat is representative of the desired fan speed.

DC motor 101 provides an output signal TACH that is indicative of theactual rotational speed of DC motor 101. This actual speed signal TACHis converted to a voltage representative of the actual motor speed by anRPM-to-voltage converter circuit 105.

PWM-to-voltage converter 103 provides an analog voltage that isproportional to the desired or required speed of motor 101.RPM-to-voltage converter 105 provides an analog voltage that isproportional to the actual speed of motor 101.

The voltage outputs of voltage converter 103 and voltage converter 105are both applied to the inputs of a difference amplifier 107 which inturn generates a control loop error voltage that is used to control amotor drive circuit 109 utilized to drive DC motor 101.

FIG. 2 illustrates controller 100 in greater detail. Converter 103includes a buffer 201 and low pass filter 203 comprising resistor R1 andcapacitor C1. Converter 105 includes frequency-to-PWM converter circuit205 and PWM-to-voltage converter 207. Converter 205 receives the speedsignal from fan motor 101 and generates a PWM signal in dependence onthe frequency of the motor speed signal. The PWM output of converter 205is applied to a second PWM-to-voltage converter 207. Converter 207includes a buffer amplifier 209 and a low pass filter 211 comprisingresistor R2 and capacitor C2. Difference amplifier 107 includes adifference amplifier circuit 213 and a low pass filter 215 comprisingresistor R3 and capacitor C3.

The prior art closed loop voltage comparison type controller 100 is ananalog closed loop arrangement. There are several problems with thistype of arrangement that are of particular concern in providing anintegrated controller. More specifically, the closed loop voltagecomparison type controller 100 requires that the Vdd supply voltagelevel to PWM-to-voltage converter 103 and PWM-to-voltage converter 207be regulated; the use of three capacitors C1, C2, C3 that add cost; andthe use of a difference amplifier 213 to produce a speed error orcorrection signal.

Turning now to FIG. 3, an improved closed loop motor controller 300 isshown in block diagram form. Controller 300 receives a PWM controlsignal corresponding to a desired motor speed at a first input 303. Theduty cycle of the PWM control signal at first input 303 is proportionalto the desired or required speed of the motor.

A tachometer feedback signal from the motor is received at terminal 305.This signal varies in frequency in proportion to the speed of the motor.The tachometer feedback signals are coupled to the input of afrequency-to-PWM converter circuit 205. Frequency-to-PWM convertercircuit 205 provides an output pulse train that has a duty cycleproportional to the actual speed of the motor. A duty cycle comparatorcircuit 307 has a first input coupled to the PWM control input terminal303 and a second input coupled to the output of the frequency-to PWMconverter circuit 205. Duty cycle comparator 307 compares the dutycycles of the signals at its two inputs and generates a control looperror voltage signal at its output 309 to the motor drive circuit.

Turning now to FIG. 4, details of duty cycle comparator 307 are shown.Duty cycle comparator 307 includes a first controllable current source311 and a second controllable current source 313 both of which arecoupled to capacitor C4. Capacitor C4 is a low pass filter that providescharge accumulation/error integration. Current source 311 is controlledby a PWM control signal and charges capacitor C4 when the PWM controlsignal is in a high state. Current source 313 is controlled by theoutput signal of the frequency-to-PWM converter 205 and dischargescapacitor C4 in proportion to the actual motor speed. Capacitor C4 actsas a charge accumulator.

FIGS. 5, 6, and 7 illustrate operation of the duty cycle comparator 307.In each of the FIGS. 5, 6, and 7, it is assumed that current sources311, 313 both supply identical current levels, I, such that currentsource 311 charges capacitor C4 with a current I and current source 313discharges capacitor C4 with current I. It is also assumed that the PWMcontrol signal is at a higher frequency than the tachometer feedbacksignal. The tachometer feedback signal is adjusted such that the dutycycle of the tachometer feedback signal, 305 a is 50% when the motor isrunning at 50% of its maximum speed.

Turning to FIG. 5, waveform 501 represents the voltage across capacitorC4, under the conditions that the desired motor speed is at 50% ofmaximum speed and the motor is operating at 50% of its maximum speed.The tachometer feedback signal is at a 50% duty cycle corresponding tohalf speed as shown by waveform 503. Under these conditions, the averagecharge and discharge current flows to capacitor C4 are equal and thevoltage across capacitor C4 is at equilibrium.

Turning to FIG. 6, waveform 601 represents the voltage across capacitorC4, under the conditions that the desired motor speed is at 75% ofmaximum speed and the motor is operating at 50% of its maximum speed.The tachometer feedback signal is at a 50% duty cycle corresponding tohalf speed as shown by waveform 603. Under these conditions, the averagecurrent flow to capacitor C4 is 0.25×I, and the voltage across capacitorC4 rises until the motor speeds up to the desired speed.

Turning to FIG. 7, waveform 701 represents the voltage across capacitorC4, under the conditions that the desired motor speed is at 25% ofmaximum speed and the motor is operating at 50% of its maximum speed.The tachometer feedback signal is at a 50% duty cycle corresponding tohalf speed as shown by waveform 703. Under these conditions, the averagecurrent from capacitor C4 is 0.25×I, and the voltage across capacitor C4falls until the motor slows to the desired speed.

There are significant advantages to utilizing duty cycle comparator 307.One such advantage is that the supply voltage Vdd does not need to beregulated because current sources are utilized. In addition, only onefilter capacitor C4 is utilized thereby saving component cost. Adifference amplifier is also not required because filter capacitor C4automatically provides the error voltage. Still further, the charge anddischarge currents do not need to be exact, but only ratio metric.

A controller 800, integrated on a single chip 801 contains all requiredfunctions for implementing fan speed control. As shown in FIG. 8, themotor controller of the invention comprising a frequency-to-PWMconverter circuit 205 coupled to the tachometer feedback signal and to aduty cycle comparator 307 integrated onto a substrate 801. Frequency toPWM converter circuit 205 includes a buffer circuit 807 coupled to thetachometer feedback terminal and edge detector 809. Edge detector 809drives one shot circuit 811. A timing circuit 813, coupled to one shotcircuit 811, comprises resistor R5 and capacitor C5. The values ofresistor R5 and capacitor C5 are selected for the maximum motor speed at100% PWM signals.

Controller 800 also includes a pulse width modulator 803 integrated onsubstrate 801. Pulse width modulator 803 comprises a fixed frequencyoscillator 805 that provides a pulse output and a saw tooth output,comparator 807, and a latch 809 along with associated gates 811 formotor speed control of motor 101. Controller 800 also includes drivercircuit 813 integrated onto substrate 801 for driving an external switchtransistor.

In other embodiments of the invention, controller 300 may be integratedonto the same silicon substrate or chip as the device being cooled byfan 101, such as Onto a microprocessor substrate.

Duty cycle comparator 307 comprises a first input 303 to receive a firstdigital signal having a first duty cycle and a second input 305 a toreceive a second digital signal having a second duty cycle. A firstcontrolled current source 311 has a control input coupled to the firstinput 303. A second controlled current source 313 has a control inputcoupled the second input 305 a. A charge accumulation device orcapacitor C4 is coupled to the first and second controlled currentsources 311, 313. The first controlled current source 311 increases thecharge accumulated by charge accumulation device or capacitor C4 inresponse to the first digital signal. The second controlled currentsource 313 decreases the charge accumulated by the charge accumulationdevice or capacitor C4 in response to the second digital signal. Chargeaccumulation device produces an output signal voltage at output 309 thatis representative of the difference in duty cycles of the first digitalsignal and the second digital signal.

In the embodiment of the invention, the first digital signal is at afirst frequency and the second digital signal is at a second frequencydifferent from the first frequency. More specifically, the firstfrequency is higher than the said frequency. However, in otherembodiments, the first and second frequencies may be equal or the firstfrequency may be lower than the second frequency.

The output signal produced by the charge accumulation device orcapacitor C4 is an analog voltage signal.

In accordance with an aspect of the invention, the embodiment provides amethod of comparing duty cycles of two digital signals as shown in FIG.9. The method comprises the steps of:

receiving a first digital signal having a first duty cycle, 901;

receiving a second digital signal having a second duty cycle, 903;

providing a charge accumulation device, 905;

controlling a first controlled current source with the first digitalsignal to charge

the charge accumulation device, 907;

controlling a second controlled current source with the second digitalsignal to discharge the charge accumulation device, 909; and

using the charge on the charge accumulation device to produce an outputsignal representative of the difference in duty cycles of the firstdigital signal and the second digital signal, 911.

It will be understood by those skilled in the art that the term “currentsource” as utilized herein includes current sources and current sinks.It will also be understood by those skilled in the art that manydifferent implementations for current sources exist and that theinvention is not dependent upon any specific implementation of a currentsource. It will also be understood by those skilled in the art thatsignal inputs 303 and 305 a can be interchanged so that a decrease inthe output voltage increases the motor speed.

The invention has been described in conjunction with a specificillustrative embodiment. It will be understood by those skilled in theart that various changes, substitutions and modifications may be madewithout departing from the spirit or scope of the invention. It isintended that all such changes, substitutions and modifications beincluded in the scope of the invention. It is not intended that theinvention be limited to the illustrative embodiment shown and describedherein. It is intended that the invention be limited only by the claimsappended hereto, giving the claims the broadest possible scope andcoverage permitted under the law.

1. A duty cycle comparator, comprising: a first input to receive a firstdigital signal having a first duty cycle; a second input to receive asecond digital signal having a second duty cycle, said second digitalsignal not having a direct relationship to said first digital signal; afirst controlled current source having a control input coupled to saidfirst input; a second controlled current source having a control inputcoupled said second input; and a charge accumulation device coupled tosaid first and second controlled current sources, said first controlledcurrent source changing in a first direction the charge accumulated bysaid charge accumulation device in response to said first digitalsignal, said second controlled current source changing in a directionopposite to said first direction the charge accumulated by said chargeaccumulation device in response to said second digital signal, saidcharge accumulation device producing an output signal representative ofthe difference in duty cycles of said first digital signal and saidsecond digital signal.
 2. A duty cycle comparator in accordance withclaim 1, wherein: said charge accumulation device comprises a capacitor.3. A duty cycle comparator in accordance with claim 2, wherein: saidfirst digital signal is at a first frequency and said second digitalsignal is at a second frequency different from said first frequency. 4.A duty cycle comparator in accordance with claim 3, wherein: said firstfrequency is higher than said second frequency.
 5. A duty cyclecomparator in accordance with claim 4, wherein: said first digitalsignal is a PWM signal and said second digital signal is a PWM signal.6. A duty cycle comparator in accordance with claim 5, wherein: saidoutput signal is an analog voltage signal.
 7. A duty cycle comparator inaccordance with claim 1, wherein: said first digital signal is at afirst frequency and said second digital signal is at a second frequencydifferent from said first frequency.
 8. A duty cycle comparator inaccordance with claim 7, wherein: said first frequency is higher thansaid second frequency.
 9. A duty cycle comparator in accordance withclaim 8, wherein: said first digital signal is a PWM signals and saidsecond digital signal is a PWM signal.
 10. A duty cycle comparator inaccordance with claim 9, wherein: said output signal is an analogvoltage signal.
 11. A duty cycle comparator in accordance with claim 1,wherein: said charge accumulation device produces said output signalrepresentative of the difference in duty cycles of said first digitalsignal and said second digital signal independent of the frequencies ofthe first digital signal and the second digital signal.
 12. A method ofcomparing duty cycles of two digital signals, said method comprising:receiving a first digital signal having a first duty cycle; receivingsecond digital signal having a second duty cycle, said second digitalsignal not having a direct relationship to said first digital signal;providing a charge accumulation device; controlling a first controlledcurrent source with said first digital signal to change, in a firstdirection, the charge accumulated by said charge accumulation device;controlling a second controlled current source with said second digitalsignal to change, in a second direction opposite to said first directionsaid charge accumulated by said accumulation device; using the charge onsaid charge accumulation device to produce an output signalrepresentative of the difference in duty cycles of said first digitalsignal and said second digital signal.
 13. A method in accordance withclaim 12, comprising: utilizing a capacitor as said charge accumulationdevice.
 14. A method in accordance with claim 13, comprising: providingsaid first digital signal at a first frequency; and providing saidsecond digital signal at a second frequency different from said firstfrequency.
 15. A method in accordance with claim 13, comprising:providing said first digital signal at a first frequency; and providingsaid second digital signal at a second frequency different from andlower than said first frequency.
 16. A method in accordance with claim15, comprising: providing said first digital signal as a PWM signal; andproviding said second digital signal as a PWM signal.
 17. A method inaccordance with claim 16, comprising: providing said output signal is ananalog voltage signal.
 18. A method in accordance with claim 12,comprising: providing said first digital signal at a first frequency;and providing said second digital signal at a second frequency differentfrom said first frequency.
 19. A method in accordance with claim 18,wherein: said first frequency is higher than said second frequency. 20.A method in accordance with claim 19, comprising: providing said firstdigital signal as a PWM signal; and providing said second digital signalas a PWM signal.
 21. A method in accordance with claim 13, comprising:providing said first digital signal at a first frequency; and providingsaid second digital signal at a second frequency different from saidfirst frequency.
 22. A method in accordance with claim 21, wherein; saidfirst frequency is higher than said second frequency.
 23. A method inaccordance with claim 22, comprising: providing said first digitalsignal as a PWM signal; and providing said second digital signal as aPWM signal.
 24. A method in accordance with claim 13, comprising:providing said first digital signal as a PWM signal; and providing saidsecond digital signal as a PWM signal.
 25. A method in accordance withclaim 12, comprising: using the charge on said charge accumulationdevice to produce an output signal representative of the difference induty cycles of said first digital signal and said second digital signal,independent of the frequencies of the first digital signal and thesecond digital signal.
 26. A method of comparing duty cycles of twodigital signals, said method comprising: receiving a first digitalsignal having a first duty cycle; receiving a second digital signalhaving a second duty cycle, said second digital signal not having adirect relationship to said first digital signal; providing a chargeaccumulation device; controlling a first controlled current source withsaid first digital signal to charge said charge accumulation device;controlling a second controlled current source with said second digitalsignal to discharge said charge accumulation device; using the charge onsaid charge accumulation device to produce an output signalrepresentative of the difference in duty cycles of said first digitalsignal and said second digital signal, independent of the frequencies ofthe first digital signal and the second digital signal.